mindspeed technologies ? 1 rs8228/m28228 errata hec error insertion failure the insert hec error function, (bit 4 of the cgen register, 0x08) may not error the hec when set high. this is due to an internal counter that inadvertently clears before reaching a count of 53. the failure occurs approximately 60% of the time. utopia fifo may lock up if an overflow is allowed to occur. the rx utopia fifo may lock up if an overflow occurs. an rx fifo overflow may occur randomly when there is a step change in bandwidth caused by a link going down and up, port configuration change, or some other condition. in this occurrence, the rxovfl bit in register 0x02e (port0) is set to a logical one which indicates that a receive fifo overflow condition occurred in the receive utopia fifo. this bit will be stuck high when the fifo is locked up and will be unable to transfer data. similarly, the transmit side may lockup. the transmit side may lockup if the transmit fifo?s are allowed to overflow. generally, this indicates that a violation of the utopia standard has occurred. workaround: to clear the lockup condition a fifo reset should be executed by setting and clearing the appropriate fifo reset bit in address 0x00d (port0). if this doesn't clear the condition, reset the port using the port logic reset bit. if this doesn?t clear the condition, then software will need to set and clear the port master reset bit, and reconfigure the port. if this doesn?t clear the condition, then software will need to set then clear the device master reset bit and reconfigure the device. clocks must be present during reset. the rs8228 is composed of 5 primary blocks: microprocessor interface, tx utopia, rx utopia, tx port, and rx port (the port blocks are duplicated 8 times; once for each port). each block uses it's own clock during the device reset. to ensure proper operation, all clocks must be present during the reset sequence and should remain active for a minimum of 3 clock cycles after the reset is cleared. this applies to all methods and levels of reset: hardware reset using the reset* pin, as well as software methods that use the device master, device logic, port master, or port logic control bits. the port clocks may be shut down or 'gapped' after the reset is finished. 500102D oct. 30, 2002
2 mindspeed technologies ? 500102D rs8228/m28228 errata de-asserting utopia rx enable during start of cell. de-asserting the utopia rx enable input, (urxenb*, pin y14), while the soc output is active may result in unpredictable behavior for that port. this should not have a major impact on customer designs since almost all utopia masters will transfer the entire cell before de-asserting the enable line.
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